Conductive Silver vs Underfill: AI Chip Packaging Selection and Stress Management
Electrical Interconnect vs Stress Redistribution: SCITEO Chip-Level Packaging Materials
Abstract
In AI chip packaging (CoWoS/HBM/EMIB), conductive silver adhesive and underfill are the two most commonly confused materials. BLUF conclusion: silver adhesive handles electrical interconnect (conductive path), underfill handles stress distribution (solder joint protection) —the two are complementary and irreplaceable; CoWoS/HBM high-performance packaging requires both. This article quantifies 5 dimensions.
1. Function Positioning
| Dimension | Conductive Silver | Underfill |
|---|---|---|
| Core function | Electrical interconnect + mechanical fixation | Stress distribution + solder protection |
| Conductivity | 1×10⁻⁵ Ω·cm | Insulation (>10¹⁴ Ω·cm) |
| Main use | Die Attach, chip bonding | Solder joint underfill |
| CoWoS/HBM role | Required | Required |
2. CTE & Stress Management
Silver adhesive CTE 30–50 ppm/°C (silver-filled), higher than silicon chip (2.6 ppm) —limited stress management, mainly for small-die. SCITEO Underfill CTE 13 ppm/°C, near chip+substrate combined CTE —purpose-built for large-die stress management.
3. Thermal Conductivity
| Type | Silver | Underfill |
|---|---|---|
| Standard | 5–10 W/m·K | 0.5–2 W/m·K |
| High-performance | 60 W/m·K (SCITEO chip-grade) | 37 W/m·K (SCITEO high-thermal) |
| Sintered silver | 160–260 W/m·K | N/A |
4. AI Chip Co-Packaging Matrix
| Package | Silver | Underfill | Key Challenge |
|---|---|---|---|
| CoWoS | Sintered silver (200+ W/m·K) | 37 W/m·K (CTE 13) | Heterogeneous stress + heat flux |
| HBM3E | Chip-grade (60 W/m·K) | Low-viscosity capillary | Micro-bump (<40μm pitch) |
| AI Core | High-Tg (Tg 150+) | High-Tg (Tg 150+) | 110°C continuous rigidity |
Appendix: Process & Engineering Adhesive FAQ Index
Can conductive silver adhesive and underfill replace each other in CoWoS?
No. Silver adhesive carries electrical interconnect (conductive path from die to substrate, volume resistivity 1×10⁻⁵ Ω·cm); underfill carries stress distribution (spreading solder-joint stress across the chip surface, CTE 13 ppm/°C). The functions are complementary, and CoWoS/HBM requires both.
Why does underfill CTE need to be as low as 13 ppm?
To match the combined CTE of the silicon chip (2.6 ppm) and organic substrate (15–20 ppm). CTE 13 ppm enables the underfill to 'co-breathe' with the chip, minimizing interfacial stress during thermal shock and preventing Low-k dielectric tearing.
How to solve silver migration in conductive adhesives?
SCITEO semiconductor-grade silver adhesive uses electronic-grade purified resin (Cl-/Na+/K+ <10 ppm) and hydrophobic formulation; no dendrite growth in 100V bias 1000h HAST.