Why Packaging Adhesives Fail Temperature Cycling and 85/85: Cracking, Damp-Heat Bias and Tg Collapse

Abstract

Why are temperature cycling (or thermal shock, as much of the industry calls it) and 85/85 damp heat so hard to pass? Adhesive reliability assessment has an old problem: the datasheet describes the state at shipment, while package lifetime is decided by the state in service. Temperature Cycling (TC, −40 °C to 125 °C, JESD22-A104F.01) and the 85/85 damp-heat bias test (THB, 85 °C/85% RH, JESD22-A101, usually accelerated on the line as pressurized HAST at 130 °C/85% RH) are the two gates nobody gets around. Failures rarely come from an unimpressive initial value. They come from non-linear degradation under extreme stress: TC amplifies thermal expansion mismatch between dissimilar materials, and 85/85 amplifies moisture uptake, hydrolysis and ion migration inside the polymer network itself.

That gives one executable threshold. A static datasheet only proves a material was good on the day it shipped. What counts is how much performance survives 1,000 cycles and 1,000 hours of damp-heat bias, and that retention decides whether the material still holds up across the whole service life.

In SCITEO's reliability laboratory, a sample is not signed off until both curves are complete, and failure analysis (FA) is built on that data. This article starts from failure chemistry and traces the real damage chain of both tests: mechanical fatigue and creep accumulation from CTE mismatch, interfacial peeling from hydrolysis, stepwise Tg depression from moisture plasticization, and insulation collapse from ion migration. It then turns those mechanisms into selection guidelines a team can execute directly, spanning semiconductor advanced packaging, automotive SiC power modules, 800G/1.6T optical modules, and military or deep-sea sensor applications.

I. The Limits of a Datasheet: Why Static Parameters Cannot Carry a Failure Call

In design reviews for advanced packaging (CoWoS, CoWoS-L, FOPLP), compute accelerators (GPU/NPU), wide-bandgap power modules (SiC/GaN) and high-precision military sensors, a set of attractive initial values tends to carry the room: shear strength, volume resistivity, storage modulus, all with what looks like comfortable margin. The disagreement usually starts the day the test chamber door opens.

Run 1,000 TC cycles (−40 °C to 125 °C) or 1,000 hours of THB, and the yield curve often bends at some unexpected point. Open the parts, and the list is familiar: wire-bond fractures, interfacial delamination, growing bond-line voids, package warpage, micro-bump cracking, C4 solder fatigue, leakage-current spikes, dielectric breakdown, and in bad cases a cracked die. These defects lie dormant at room temperature; only extreme stress forces them out, one tier at a time.

The question customers ask most often is this: initial strength looked sufficient, so why does it still delaminate? The answer usually is not in the parameter table but in the failure chain. Many approaches treat packaging adhesive as a static physical filler, yet at a real micro-scale interface it does two jobs at once: it gives heat a low-resistance path, and it blocks the paths that stress and ions would otherwise take. Misread that dual role and every downstream parameter discussion loses focus. SCITEO's application team works continuously inside 2.5D/3D packaging, high-power SiC module and military sensor production lines. What follows is the specific failure path of that dual role.

The final call usually rests on the intersection of three data sets: mechanical shear retention (measured to GB/T 7124), thermomechanical Tg, CTE and storage modulus (measured by DMA and TMA), and electrical volume resistivity plus surface insulation resistance (SIR). All three curves have to run through the same chamber on the same schedule before a selection decision holds. That is where physics-of-failure (PoF) selection and datasheet selection part ways.

II. Temperature Cycling: From CTE Mismatch to Creep Accumulation

TC testing (JESD22-A104F.01) is not about cold or heat on their own. What does the work is the strain-rate differential created by violent temperature swings, plus the viscoelastic strain that piles up during dwell. Silicon, organic substrates, metal leadframes and ceramic bases differ widely in CTE, and the adhesive layer trapped between them has to absorb tear-level micro-shear. Damage per cycle is too small to measure; only after a few hundred cycles do creep and fatigue add up into a macroscopic crack.

One distinction deserves to be drawn first, because the two are routinely conflated. Thermal Shock (TS) is governed by strain rate: it drives a temperature gradient across the part in seconds, typically liquid-to-liquid or in a fast air chamber, and stresses brittleness and short-term tensile capability. Temperature Cycling is governed by strain time and accumulated strain: every extreme carries a dwell measured in minutes, and an adhesive with insufficient modulus keeps relaxing through that dwell, banking damage cycle after cycle. Different driving quantities mean the two data sets cannot substitute for each other.

Advanced Packaging (2.5D/3D): Why Micro-Bumps Shear Off After Cycling

As compute chips move to chiplets and 3D heterogeneous integration, the package itself has become the physical boundary of compute supply. In high-density interconnect architectures, micro-bump pitch between die and interposer has narrowed to the micrometer range.

When TC drops from 125 °C to −40 °C, the silicon die (CTE ≈ 2.6 ppm/°C) barely moves while the organic substrate beneath it (CTE typically 15-20 ppm/°C) contracts hard. The underfill is there to buffer that, but a poorly designed Tg or a high CTE means it absorbs nothing and hands the shear straight to the micro-bumps: solder fatigue, cracking, then full separation. A second failure mode gets missed often: low-temperature embrittlement. Once modulus spikes non-linearly in the cold, the buffer layer becomes a rigid cutting edge and severs micrometer-scale metal interconnects.

HBM stacking tightens the constraint further. JEDEC raised the HBM4 total package thickness ceiling from 720 μm to 775 μm, a figure that roughly matches the thickness of a 300 mm logic wafer: one cold plate has to seat both the logic die and the memory stack beside it, and a taller memory cube would stand proud of the processor next to it. A 16-Hi stack must thin its core dies to roughly 50 μm and nearly halve the die-to-die gap, which is how HBM4 reaches 48 GB per 16-Hi cube; 12-Hi remains the volume workhorse for now. Thinner dies leave proportionally more oxide in the stack, and oxide conducts heat far worse than silicon, so heat and stress are compressed into a thinner stack; industry figures put the cumulative thermal burden about 2.2x higher than early generations, while per-pin speed has climbed from the 1 Gbps class to 8 Gbps. Thinner stacks are harder to keep flat, the fill window narrows with them, and warpage is now the main yield limiter for 16-Hi production.

Hybrid bonding removes inter-die micro-bumps and gap-fill by joining Cu to Cu directly, cutting interconnect thermal resistance and parasitics in one step. It relies on an anneal above roughly 200 °C so copper expands to close the recess, which imposes far stricter demands on interfacial CTE consistency and cure behavior than conventional packaging. Timing is worth watching: with the 775 μm ceiling relaxed, leading suppliers still cover HBM4E with MR-MUF and are pushing copper-to-copper bonding further out, while JEDEC discusses a further relaxation of the HBM5 (20-Hi) thickness ceiling to 900-1000 μm. More thickness headroom lowers the urgency of hybrid bonding for thinning, so the stress window for interface materials stays largely on the MR-MUF path in the near term, and the underfill fill window plus warpage control has to carry the load.

Automotive SiC Power Modules: Where Pump-Out Actually Comes From

In EV control units and 800 V traction inverters, SiC MOSFET junction temperatures routinely exceed 175 °C, and AQG 324-qualified automotive modules now list 200 °C junction temperature as a short-duration capability. Layering power cycling on top of TC puts the packaging material under two questions at once: whether the interface can hold a thermal path through hundreds of excursions, and whether the material itself keeps losing mass or turning to powder at temperature.

After a few hundred cycles, the adhesive expands and contracts repeatedly between temperature extremes, the interface shifts at the micro scale, conductive filler agglomerates, and the adhesive is eventually squeezed out of the interfacial gap. That is what the industry calls pump-out. Once pump-out or micro-delamination occurs, interfacial thermal resistance rises fast; heat no longer reaches the heatsink, and the device usually ends in thermal runaway. Per-package power in mainstream SiC modules keeps climbing, which makes this problem sharper, not softer.

Changes in the die-attach layer are also rewriting the order of the failure chain. Sintered silver forms a continuous silver skeleton at 250-300 °C under pressures from a few megapascals to several tens of megapascals, reaches thermal conductivity of 240-260 W/m·K, and shows almost none of the creep and recrystallization fatigue that solder exhibits under thermal cycling. Sintered copper costs less and carries lower ion-migration risk, and pressure-assisted copper sintering now pulls temperature down to 200-250 °C and pressure to 10-15 MPa while still exceeding 300 W/m·K. For interface materials this redefines the role: no longer the sole structural load path, but a layer that must respond in step with the sintered joint, the AMB ceramic substrate (Si₃N₄ at roughly 3.2 ppm/°C) and the copper heatsink.

800G/1.6T Optical Modules: Optical Path Drift

As bandwidth density climbs, the laser (TOSA) and receiver (ROSA) inside an optical module sit under sustained heat. Then a reboot, or a power cut at a sub-zero base station, drops the temperature within minutes.

Traditional silicones often exceed 200 ppm/°C in CTE, producing substantial volumetric shift during thermal cycling; standard epoxies go the other extreme, turning brittle and losing elasticity in the cold. When SCITEO reproduced the 800G/1.6T module case, neither material buffered the stress between quartz glass and the metal housing: the optical path drifted by micrometers and the signal dropped out. For a link carrying safety redundancy, that failure mode has no acceptable probability. As co-packaged optics (CPO) moves the optical engine inside the package, interface materials must also withstand higher local heat flux and stricter low-outgassing limits, and the stress-buffer window left to the adhesive narrows further.

Low Modulus Is Not a Universal Answer: The Creep Trap

A widely held intuition says thermal stress should be absorbed by a soft enough adhesive. At micrometer-scale precision manufacturing, that intuition tends to fail.

Over repeated thermal cycling, an overly compliant material accumulates serious creep. The polymer loses resilience through round after round of stress relaxation until the internal support collapses. SCITEO takes the opposite direction: build a high-modulus rigid support network (4.2 GPa, up to 9-13 GPa) and lock the whole structure with ultra-low CTE plus strong cohesion. Rather than absorbing stress passively, the material resists micro-displacement through high interfacial shear strength (> 25 MPa), holding strength loss near zero after 1,000 cycles between −40 °C and 125 °C.

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III. 85/85 Damp-Heat Bias (THB/HAST): Electrochemical Migration and Tg Collapse

Damp heat attacks through three lines running in parallel: interfacial hydrolysis and peeling, stepwise Tg depression from moisture plasticization, and electrochemical migration with dendritic growth of mobile ions under bias. Together they decide how much insulation capability and bond strength survive 1,000 hours, and whether the same question should be forced out earlier with pressurized HAST.

Reviewing failed 85/85 parts, SCITEO's R&D team keeps returning to the same thread: what the material gives up is rarely the insulation value it shipped with, but the few degrees of Tg that move once the network takes on water. Every short and delamination downstream starts there.

Sensors and Deep-Sea Potting: Why Insulation Collapses Within Hundreds of Hours

Sealing layers in military sensors and deep-sea probes must hold stable electrical insulation through salt fog or sustained moisture. Atmospheric 85/85 (with a national-standard counterpart in GB/T 2423.3 / IEC 60068-2-78 steady-state damp heat), pressurized HAST, and surface insulation resistance (SIR) monitoring are normally run in parallel.

Hydrolysis is the first problem conventional epoxy and polyurethane systems meet under 85/85. Moisture enters the polymer through its free-volume network. If the formulation retains unreacted free acids, halide ions (Cl⁻), or alkali metal ions (Na⁺, K⁺), water becomes an efficient carrier for them. Under bias, those ions migrate directionally and form conductive pathways, and the volume resistivity printed on the datasheet falls by several orders of magnitude within a few hundred hours, showing up as sensor shorts, micro-current leakage, or logic misfires. If moisture reaches the metal interface, the electric field also catalyzes silver and copper ion migration, growing dendritic filaments along the moisture path until they pierce the dielectric and cause an irreversible internal short. Inside organic substrates and laminates, the same humidity-bias combination drives conductive anodic filament (CAF) growth, whose channel runs along the glass-resin interface where visual inspection and routine electrical test rarely catch it in time; it usually surfaces only after insulation resistance has already dropped.

Interfacial Hydrolysis: How Adhesion Is Actually Lost

Electrical damage is only the first layer. Moisture is equally the terminator of interfacial adhesion. On copper, aluminum or glass, water molecules occupy surface hydroxyls first, competing with the adhesive's polar groups and forming a microscopic water film; once the chemical bonds a silane coupling agent built at the interface are hydrolyzed, only van der Waals forces remain.

Sustained 85 °C baking then vaporizes and expands that film, generating enormous localized vapor pressure at the interface, enough to lift the entire adhesive layer off the substrate. Interfacial voids amplify this chain: micro-pores left by cure shrinkage or trapped during dispensing are already water reservoirs, and once heated, the vapor pressure inside them far exceeds that of the surrounding polymer, so delamination tends to initiate at void edges. The failure usually starts inside that invisible layer of water. It is why interfacial delamination became a standard packaging reliability check, inspected by scanning acoustic microscopy (C-SAM) against IPC/JEDEC J-STD-035.

Plasticization and Tg Depression: An Underestimated Cascade

For outdoor sensors and modules in long-term high-humidity service, a quieter problem is also the harder one: moisture plasticizes the polymer and pulls glass transition temperature (Tg) down in one step. An adhesive with an original Tg of 145 °C can fall to 105 °C once saturated.

The consequences cascade. When the device runs at full load in summer heat with internal temperatures at 120 °C, or passes through reflow soldering later, the actual temperature has already crossed the depressed Tg. CTE then runs from 30 ppm/°C to over 100 ppm/°C, and residual moisture flashes into vapor; add the popcorn effect and a die can crack from the inside within seconds. Damp-heat reliability is therefore read from the saturated wet Tg (measured by DMA, logging the tanδ peak position and storage modulus alongside it), not from the Tg printed at shipment; equilibrium water absorption and the coefficient of hygroscopic expansion (CHE) set how far that Tg moves, and reflow preconditioning follows the moisture sensitivity level of IPC/JEDEC J-STD-020.

HAST Acceleration and Lifetime Extrapolation

The atmospheric 85/85 test (JESD22-A101) uses 1,000 hours as its standard duration. Biased HAST (bHAST, JESD22-A110) reproduces the same electrochemical corrosion and ion-migration stress in 96 hours at 130 °C, 85% RH and roughly 2.3 atm of saturated steam pressure, about a 10x time compression. Unbiased HAST (uHAST, JESD22-A118) surfaces interfacial delamination and moisture-induced cracking earlier. Automotive qualification (AEC-Q100 Rev-J/J1) accepts HAST as an equivalent substitute for THB under the JESD47 framework, raises the Grade 0 ambient ceiling to −40 °C to +150 °C, runs temperature cycling to JESD22-A104 between −55 °C and +150 °C, and adds a post-cycle delamination data requirement.

The test can be accelerated; the conclusion cannot skip a step. Lifetime extrapolation has to count both the temperature term and the humidity term, because a conversion that varies temperature while ignoring humidity will systematically overstate service life. More important still, the acceleration stress must not cross the material's wet Tg, or the failures it provokes will never reproduce under atmospheric service conditions. SCITEO keeps both the atmospheric 85/85 curve and the pressurized HAST curve in its data matrix to cross-validate the independence of ion migration and interfacial hydrolysis.

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IV. Reliability Guidelines in Structured Comparison

Placing the driving mechanisms and material countermeasures in one table makes it much clearer which quantities the selection decision should track.

V. Material Design: Working at the Formulation Gene Level

Fighting the combined attack of moisture and heat with an external coating is wasted effort; water eventually diffuses along the interface to the bond line. There is one viable path: change the formulation at its genetic level.

Precision Balance Between Ultra-Low CTE and Dynamic Modulus

Countering shear in TC is not a matter of harder or softer. SCITEO's approach is to control polymer phase reconfiguration: below Tg the material holds an ultra-low CTE (< 25 ppm/°C) so it deforms in step with silicon wafers and ceramic substrates, keeping micro-stress stable, while the modulus system keeps a toughness margin in reserve. Between −40 °C and −60 °C the material is not permitted to embrittle; it must dissipate stress through micro-slip of polymer chains and protect fragile structures such as micro-bumps and TSVs.

Take SCITEO's 5 W/m·K thermal epoxy system as an example. A 13 ppm/°C ultra-low CTE and a 13 GPa modulus hold inside the same formulation, and 32 MPa initial shear strength retains over 90% after 1,000 TC cycles, corresponding to roughly 29 MPa of interfacial load capacity. Numbers like these only carry selection weight when the TC and 85/85 retention curves converge together.

Ionic-Level Purity and a Dense Crosslinked Network

Against insulation failure and ion migration under 85/85, the priority is to cut off the carriers at their source. SCITEO electronic-grade packaging materials use stringent purification during synthesis, holding halogens and free alkali-metal ions at very low levels (Cl⁻/K⁺ < 0.8 ppm, quantified by ion chromatography). A highly crosslinked molecular network then compresses the physical permeation path for water, keeping absorption below 0.03%. Cure shrinkage is an equally early indicator: held below 0.2% per ISO 2577, it prevents the interface from being pulled open during crosslinking, which would otherwise leave a moisture path in place before testing even begins. Even after 1,000 hours of 85 °C/85% RH bias, the material still holds a high-impedance state of 10¹³ Ω·cm.

Thermal Reconfiguration for Extreme Duty

Whether the requirement is continuous 300 °C service in quartz or ceramic packaging, or encapsulation for compute chips that see 200 °C-class hotspots under a weight-loss constraint, the real blocker lands in the same place: where the cured network's Tg sits. Filler size and viscosity can be tuned; Tg is set by main-chain structure and crosslink topology.

The logic is direct. While service and process temperatures stay below Tg, chain segments are frozen in the glassy state and the material holds three things at once: low CTE (13-30 ppm/°C), a stable storage modulus, and negligible creep. Cross Tg and CTE climbs from 30 ppm/°C to beyond 100 ppm/°C, modulus drops away, and interfacial displacement plus pump-out start to accumulate from that moment. Tg, in other words, is the margin the system reserves for 260 °C reflow dwell, 250-300 °C sintering-adjacent steps and 200 °C-class continuous duty.

The industry has already pushed that line to 230 °C: solid epoxy encapsulation aimed at next-generation SiC power modules has reached a 230 °C Tg and entered mass production. The hard part is lifting Tg without lifting modulus along with it. Higher crosslink density raises interfacial stress, which makes delamination and cracking more likely, so high Tg and low stress have long been a trade-off.

SCITEO's answer lives in the main chain and the crosslink topology: rigid segments lift Tg, while a controlled crosslink distribution and low-stress architecture hold the elastic modulus down, so that Tg can step up with the duty cycle, with ample headroom above 200 °C, while the sub-Tg CTE and modulus stay locked inside a window that does not load the interface. The dispensing process is designed against the same target: the dispense window's viscosity and flow must fill sub-millimeter gaps, and the cure profile must let the network develop fully so the Tg in the formulation is actually grown rather than only printed on a datasheet. Aligned, the material neither carbonizes nor pulverizes after long-term high-temperature aging, the bond interface and thermal path stay intact, and pump-out and thermal-resistance decay are eliminated at the source.

VI. Beyond the Classic Envelope

The boundary of a reliability test is rarely drawn by the standard itself. It gets pushed around by package architecture and service environment. Several shifts now underway have already made the classic TC and 85/85 envelopes feel insufficient.

Kilowatt-Class Heat Flux: Modulus, Bond Strength and Insulation Have to Hold Together

3D stacked architectures trap heat sources between die layers, where inter-layer dielectrics conduct poorly. Even with external liquid cooling, peak temperatures inside the stack can approach 150 °C; localized hotspot heat flux above 1000 W/cm² and package-level TDP past 500 W are no longer rare on high-end compute chips. The question is no longer a temperature rating, but whether modulus, bond strength and insulation resistance can stay stable together under kilowatt-class heat flux and high-voltage bias. None of the TC or 85/85 test items have gone away; every one of them has less margin left.

Deep Cryogenics: The Mirror-Image Problem at Millikelvin

Superconducting qubits operate in the 10-20 mK dilution-refrigerator range, while chip-scale photonic approaches run at around 1.55 K on closed-cycle cooling. Interfacial materials in the liquid-helium domain must answer three questions at once: extreme low-temperature embrittlement, multi-material CTE mismatch, and ultra-low outgassing, assessed to the ASTM E595 total mass loss and CVCM criteria. Their stress logic is a mirror image of the 85/85 damp-heat logic: one regime is dominated by moisture uptake and ion migration, the other by thermal contraction differentials and cryogenic brittleness, while both demand identical purity and interfacial integrity. Conventional organic polymer adhesives tend to crack, outgas, or lose optical alignment under deep cryogenic, high-radiation and ultra-high-vacuum conditions, which is why inorganic bonding routes such as hydroxide catalysis bonding (HCB) are re-entering packaging process discussions.

New Substrates and Interconnects: Interface Chemistry Becomes the Blocker Again

Glass-core substrates and panel-level packaging integrate TGV (through-glass vias), fine-pitch RDL and embedded bridges into one carrier, and their tunable CTE (3-10 ppm/°C, against silicon's 2.6 ppm/°C), low dielectric loss and surface flatness make them the candidate platform for large-format AI compute packages. New substrates bring new interfacial problems: glass is chemically inert, so conventional coupling systems struggle to form stable bonds, while TGV and RDL copper filling requires encapsulants that resist delamination and outgassing after high-temperature processing. At the same time, bridge packaging with TSV-based power delivery keeps pushing bump pitch down, further shrinking the stress-buffer window left to interface materials. What these problems share is that swapping in a different adhesive does not solve them; the interface chemistry and the process window have to be designed together.

A useful reliability framework has to extend to new temperature domains, new power densities and new substrate platforms; a framework that only supplies fixed thresholds will age out along with the package architecture. SCITEO's application team will keep tracking and validating these directions.

VII. From Failure Chain to Process Window

In the micro-scale world of packaging, reliability is ruled by physics and chemistry, and initial parameters guarantee nothing. TC cycling and 85/85 (THB/HAST) testing are the industry's quantitative probe of a material's limit boundary: what they deliver is not a certificate of compliance, but an extrapolatable degradation curve.

In project work, we translate the failure chain above into a set of checkable process windows: interfacial stress against CTE, modulus and Tg margin; damp-heat hydrolysis against water absorption, ionic purity and cure shrinkage; insulation degradation against wet Tg and volume-resistivity retention; long-term heat against thermal weight loss and the temperature ceiling. Only when all four windows hold does a material really stand a chance of defending its performance through the service life. High-end manufacturing no longer lacks general-purpose adhesives; it lacks an engineering logic of physical parameters that can be rigorously verified, and SCITEO connects the reliability data matrix from its R&D laboratory directly to the customer's selection review, so every conclusion carries traceable measured support.

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