Underfill Selection Guide: AI Compute Chips & CoWoS Advanced Packaging Thermal Adhesive White Paper
37W/m·K Thermal & 13ppm Ultra-Low CTE: SCITEO Chip-Level Stress Management Guide
Executive Summary
The explosion of Generative AI and HPC has driven NVIDIA H100/Blackwell, AMD MI300, and Google TPU toward 2.5D/3D packaging —CoWoS, EMIB, HBM. Underfill has evolved from "flow & fill" to "stress redistribution" and "active thermal conduction." This article analyzes how SCITEO's 13 ppm ultra-low CTE and 37 W/m·K thermal conductivity solve high-compute chip packaging reliability.
1. Packaging Transformation in the Compute Era
Whether NVIDIA GPU clusters or Google TPU matrices, CoWoS and EMIB integrate HBM3E with logic compute units. Engineering challenge: CTE mismatch between heterogeneous chips, micron-scale bump pitch (<40μm), and hundreds of watts of dissipation place unprecedented demands on Underfill —balancing high flowability with high thermal conductivity.
2. How Underfill Eliminates Packaging Failure
Silicon dies (CTE 2.6 ppm/°C) and organic substrates (CTE 15–20 ppm/°C) exhibit complex CTE mismatch. During reflow or AI workload thermal cycling, this converts into massive shear stress tearing fragile Low-K dielectric layers or solder joints.
Stress Decoupling & Solder Joint Protection: Underfill penetrates via capillary flow, forming a high-modulus crosslink network upon cure. Mechanically couples to disperse thermal stress concentrated on solder joints across the entire die surface. In mobile devices, absorbs dynamic drop-impact stress.
Barrier Construction: Builds a zero-void hermetic layer, blocking moisture ingress and preventing ECM shorts under bias.
Thermal Enhancement: SCITEO thermally-conductive Underfill as auxiliary heat dissipation medium.
3. SCITEO Underfill Technical Parameters
CTE Precision: SCITEO low-CTE series achieves CTE <30 ppm/°C, critical for large-die packaging.
Tg: High-Tg series exceeds 150°C —material remains rigid throughout operating temperature range.
The "Impossible Triangle" Breaker: SCITEO 37W/m·K Underfill: CTE 13 ppm/°C (near-equal to substrate + die), Tg 150°C, shear 32 MPa (standard: 10–15 MPa). Ideal for large AI chip packaging.
4. Application Scenarios
| Application Scenario | Key Challenge | SCITEO Solution |
|---|---|---|
| WLP | Ultra-low warpage | Low CTE (<30 ppm), high modulus, low shrinkage |
| CoWoS/HBM | Heterogeneous integration stress | High Tg (>130°C), silicon interposer matched |
| AI Core/HPC | Extreme heat flux, hotspot elimination | 37W/(m·K) thermal, CTE 13, 32 MPa |
| Rework | Expensive chip recovery | Reworkable series |
5. Future Vision
SCITEO will continue investing in high-thermal (50W+), low-CTE (<20 ppm), and ultra-low-temp cure (50°C) R&D. We track NVIDIA Blackwell architectures, silicon photonic interconnects, and 6G chips —providing the most robust material foundation for sustaining Moore's Law in three dimensions.
Appendix: Process & Engineering Adhesive FAQ Index
How to select the right Underfill viscosity?
Viscosity depends on bump pitch and chip-to-substrate gap height. The smaller the gap, the lower the viscosity required for smooth capillary flow. SCITEO offers multiple viscosity grades for different processes.
What are SCITEO Underfill curing conditions?
We recommend step curing to minimize thermal stress. Specific profiles are customized based on chip size and substrate material, typically completed within the 100–150°C range.
Can Underfill be used with conductive silver adhesive?
Yes. SCITEO has a full semiconductor-grade adhesive portfolio. Our Underfill and conductive silver die-attach have been compatibility-tested. Both feature low-CTE properties, and combined use further improves overall module reliability.